Performances of the AES design in 0.18μm CMOS technology
Hassen Mestiri, Mohsen Machhout, Rached Tourki · 2012
The Advanced Encryption Standard (AES) has been studied by designers with the goal to improve its performances in terms of area, power consumption and frequency. In this paper, we present the implementation details of the AES encryption 128-bit, the MixColumns transformation and the SubBytes transformation. The latter can be implemented using a multi-stage PPRM architecture and composite field arithmetic in GF(((22)2)2). In addition, the MixColumns transformation is used in two architectures. The AES algorithm is implemented using 1.8V 0.18μm Complementary Metal Oxide Semiconductor (CMOS) technology. A low power consumption of 24.92 μW at 10 MHz and 23.2 mW at 67 MHz were achieved for the multi-stage PPRM architecture of SubBytes transformation and the AES encryption respectively. Compared to previous works, our AES implementations achieve good performance in term of power consumption.