An SoC integrating an H.264 encoder with an ISP
Eung Sup Kim, Seongyoon Kim, Gyounghwan Hyun, Jin-Su Jung, Chae Eun Rhee, Yongseok Jin, Hyuk‐Jae Lee · 2009
The SoC presented in this paper integrates an H.264 encoder with an ISP (Image Signal Processor). It is currently implemented in an FPGA and processes an HD-size (1280 × 720) image at the speed of 15 fps with the operating clock frequency of 50 MHz. In the presented demo system, a Bayer input from a CMOS image is given to the FPGA and the output stream is transmitted through an USB transceiver to a PC that decodes and displays the H.264 stream.