An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory
S. O'Kane, Siren Sezer · 2005
The asynchronous nature of packet based communication demands efficient management of buffer resources at network nodes. Shared buffer architectures consequently become one of the dominating constructs of modern routers and switches. This work investigates new and existing shared buffer architectures that are ideal for emerging FPGA technologies with embedded memory.