Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm
Jui-Yuan Hsieh, Shanq-Jang Ruan · 2008
Abstract — Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using paral-lel comparison to reduce search time. Although the use of par-allel comparison results in fast search time, it also significantly increases power consumption. In this paper, we propose a gate-block selection algorithm, which can synthesize a proper param-eter extractor of the pre-computation-based CAM (PB-CAM) to improve the efficiency for specific applications such as embedded systems. Through experimental results, we found that our ap-proach effectively reduces the number of comparison operations for specific data types (ranging from 19.24 % to 27.42%) com-pared with the 1’s count approach. We used Synopsys Nanosim to estimate the power consumption in TSMC 0.35um CMOS pro-cess. Compared to the 1’s count PB-CAM, our proposed PB-CAM achieves 17.72 % to 21.09 % in power reduction for specific data types. I.