Testability trade-offs for BIST RTL data paths: the case for three dimensional design space
Nicola Nicolici, B.M. Al-Hashimi · 2001
Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testabil-ity trade-offs in terms of test application time, BIST area overhead and power dissipation. It was reported in [4] that there is significantly higher switching activity during testing than during functional op-eration and hence higher power dissipation. The aim of this paper is to examine testability trade-offs for built-in self-testable (BIST) register-transfer level (RTL) data paths, and based on exhaustive experimental data to justify the need for a three dimensional testable design space which needs to be considered while exploring alternative solutions. The experimental validation flow is employed for 32