An integrated 802.11a baseband and MAC processor
John Thomson, Bevan M. Baas, E.M. Cooper, Jeffrey M. Gilbert, G. Hsieh, Paul Husted, A. Lokanathan, Jeffrey S. Kuskin, Daniel D. McCracken, Bill McFarland, T.H. Meng, D. Nakahira, S. Ng, M. Rattehalli, Justin L. Smith, Ramanathan Subramanian, L. Than, Yi-Hsiu Wang, Rui Yu, Xiaoru Zhang · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2005
The tremendous growth in wireless LANs has generated interest in technologies that provide higher data rates and greater system capacities. The IEEE 802.11a standard, based on coded OFDM modulation, provides nearly five times the data rate and as much as ten times the overall system capacity as current 802.11b wireless LAN systems [1,2,3]. This baseband and MAC processor is part of a two-chip set that forms a complete 802.11a solution [4]. The chip operates up to 54Mb/s in 20MHz channels according to the 802.11a standard, and includes proprietary modes supporting up to 108Mb/s in 40MHz channels. Figures 7.2.1 and 7.2.2 depict the system and MAC architecture. The protocol control unit (PCU) manages all low-level, timingcritical aspects of 802.11. It formats and sends outgoing frame data to the baseband transmitter and processes incoming frame data from the baseband receiver. The host interface unit (HIU)