A Pipeline Chip for Quasi Arithmetic Coding
Yair Wiseman · IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences · 2001
SUMMARY A combination of a software and a systolic hardware implementation for the Quasi Arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn’t change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of the compression efficiency.