On concurrent error detection, location, and correction of FFT networks
C.G. Oh, Hee Yong Youn · 2002
Fault tolerance has been a major issue for the VLSI based FFT networks. A new concurrent error detection, location, and correction scheme for FFT networks is proposed. By using an effective checksum scheme, the design allows high throughput as well as high fault coverage. Computer simulation reveals that the fault coverage is 100% with a very small false-alarm rate. The hardware overhead is as small as 1/log/sub 2/N. A faulty component can also be located by two tries and log/sub 2/m comparisons of m corrupted outputs. More importantly, the design can correct an error at a small modification of the basic structure. The design is also shown to be easily expanded for multidimensional FFT networks.