A 64x64 cell mixed-mode array processor prototyping system
Mika Laiho, Jonne K. Poikonen, Peter Virta, A. Paasio · 2008
This paper introduces a 64x64 cell massively parallel processor array and measurement system. The approach taken in the chip is based on the inclusion of dedicated computing cores, each of which have been designed to implement a specific set of operations very efficiently. The chip can be roughly divided into two grayscale processing cores, one for order statistic filtering and the other for absolute-value-based operations, a binary processing core, and associated in-cell memories and data converters. In addition to the versatile in-cell hardware, the chip also has an advanced row/column decoder setup which can be used e.g. for scalable region of interest processing.