An Improved FPGA Implementation of the Modified Hybrid Hiding Encryption Algorithm (MHHEA) for Data Communication Security
Hala A. Farouk, Magdy M. Saeb · Design, Automation, and Test in Europe · 2005
The hybrid hiding encryption algorithm, as its name implies, embraces concepts from both steganography and cryptography. An improved micro-architecture field programmable gate array (FPGA) implementation of this algorithm is presented. This design overcomes the observed limitations of a previously-designed micro-architecture. These observed limitations are: no exploitation of the possibility of parallel bit replacement; the fact that the input plaintext was encrypted serially, which caused a dependency between the throughput and the nature of the used secret key. This dependency can be viewed by some as a vulnerability in the security of the implemented micro-architecture. The proposed modified micro-architecture is constructed using five basic modules: the message cache; the message alignment module; the key cache; the comparator; the encryption module. We provide comprehensive simulation and implementation results. These are: the timing diagrams; the post-implementation timing and routing reports; the floor plan. Moreover, a detailed comparison with other FPGA implementations is made available and discussed.