Efficient FIR filter architectures suitable for FPGA implementation
Joseph Evans · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 1994
This paper describes efficient architectures for FIR filters. By exploiting the reduced complexity made possible by the use of two powers-of-two coefficients, these architectures allow the implementation of high sampling rate filters of significant length on a single field-programmable gate array (FPGA).>