PRET DRAM controller
Jan Reineke, Isaac Liu, Hiren Patel, Sung Jun Kim, Edward A. Lee · 2011
Hard real-time embedded systems employ high-capacity memories such as Dynamic RAMs (DRAMs) to cope with increasing data and code sizes of modern designs. However, memory controller design has so far largely focused on improving average-case performance. As a consequence, the latency of memory accesses is unpredictable, which complicates the worst-case execution time analysis necessary for hard real-time embedded systems.