An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication
Jochen Strunk, Toni Volkmer, Wolfgang Rehm, Heiko Schick · 2009
In this paper a low latency, on chip communication network (NoC) for a run-time reconfigurable (RTR) grid inside dynamically and partially reconfigurable (DPR) FPGAs is proposed, which supports the arbitrary placement of run-time reconfigurable modules (RTRM) inside the grid. The dedicated, fully meshed, silicon network should support the arrangement of communication channels between the RTRMs within the different partially reconfigurable regions (PRRs) on the FPGA. The design of the network guarantees a low latency communication of RTRMs without mutual interference of each other. In comparison with an implementation using FPGA resources the dedicated silicon network could save an huge amount of resources in terms of transistors. The new degree of parallel communication provided for a RTR grid with arbitrarily placeable RTRMs offers new application fields for DPR capable FPGAs. Multiple user applications with inter-communicating offload compute kernels can be loaded on a host coupled FPGA accelerator, a real-time (RT) system with concurrent communication tasks are possible and enhancing the functionality on demand for embedded systems is conceivable. A case study was conducted for proof of concept and for the verification of the run-time environment system, which manages the configurable network.