A 100MHz ASIP (application specific instruction processor) for CAVLC of H.264/AVC decoder
Jun-Young Lee, Jaejin Lee, MooKyoung Jeong, Nak-Woong Eum, Seongmo Park · 2008
In this paper, we implement the configurable processor for CAVLC function module of a H.264/AVC baseline profile decoder as the starting point to implement the H.264/AVC decoder system in a multiprocessor platform. The requirements of the implementations are the low-power processor and speed optimized algorithms tailored to the processor architecture. An arithmetic formula mapping method for fast CAVLC algorithms and a dual-issue VLIW processor architecture with custom instructions are proposed. The experiment results show that the synthesized processor has about 75 K gates and can carry out the decoding of 30-fps CIF (352x288 pixels) images around 120 Mega cycles.