Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC
Vason P. Srini · 2005
Rapid prototyping and simulation of digital systems using mays of field programmable gate array (FPGA) chips is expected to be an important aspect of digital design and implementation. Four classes of architectures are discussed for connecting an array of FPGA chips and also logic blocks in a chip to achieve functionality and performance comparable to that of ASIC designs using standard cells and mask programmable gate arrays and at a low cost and reduced development time. The four classes of architectures use technologies such as antifuse, SRAM, Electrically Erarable PROM (EEPROM), and (Ultraviolet) Erasable PROM (EPROM) to control and configure interconnection structures between the logic blocks. The software requirements for these classes of architectures and potential performance are discussed. The impact of these architectures on commercial products is also described.