A VHDL-based methodology for designing a Prolog processor
José Jaime Ruz, A. Sadaoui, Alvaro Ruiz-Andino · 2002
The paper presents a VHDL-based simulation methodology used to design a special-purpose processor for executing Prolog programs. The presented approach allows functional verification of the design at behavioral, register transfer and structural levels as well as performance evaluation. Two logic programming formal tools are used for automatic translation and optimization from the first level through the last level: definite clause grammars (DCGs) and constraint logic programming (CLP).>