A 600-MHz Single-Chip Multiprocessor With 4.8-GB/s Internal Shared Pipelined Bus and 512-kB Internal Memory
Satoshi Kaneko, Hiroyuki Kondo, Norio Masui, Koichi Ishimi, Toshiyuki Itou, M. Satou, Naoto Okumura, Yukari Takata, H. Takata, Mamoru Sakugawa, T. Higuchi, S. Ohtani, Kazuki Sakamoto, Naoki Ishikawa, Masumi Nakajima, S. Iwata, K. Hayase, Shinya Nakano, S. Nakazawa, K. Yamada · IEEE Journal of Solid-State Circuits · 2004
A 600-MHz single-chip multiprocessor, which includes two M32R 32-bit CPU cores , a 512-kB shared SRAM and an internal shared pipelined bus, was fabricated using a 0.15-/spl mu/m CMOS process for embedded systems. This multiprocessor is based on symmetric multiprocessing (SMP), and supports modified-exclusive-shared-invalid (MESI) cache coherency protocol. The multiprocessor inherits the advantages of previously reported single-chip multiprocessors, while its multiprocessor architecture is optimized for use as an embedded processor. The internal shared pipelined bus has a low latency and large bandwidth (4.8 GB/s). These features enhance the performance of the multiprocessor. In addition, the multiprocessor employs various low-power techniques. The multiprocessor dissipates 800 mW in a 1.5-V 600-MHz multiprocessor mode. Standby power dissipation is less than 1.5 mW at 1.5 V. Hence, the multiprocessor achieves higher performance and lower power consumption. This paper presents a single-chip multiprocessor architecture optimized for use as an embedded processor and its various low-power techniques.