Testability improvement during high-level synthesis
Saeed Safari, Esmaeilzadeh, Amir Hossein Jahangir · 2003
Improving testability during the early stages of High-Level Synthesis (HLS) reduces test hardware overheads, test costs, design iterations, and also improves fault coverage. In this paper, we present a novel register allocation algorithm which is based on weighted graph coloring, targeting testability improvement.