Modeling Microprocessor Faults on High-Level Decision Diagrams
Raimund Ubar, Jaan Raik, Artur Jutman, Maksim Jenihhin, Martin Instenberg, Heinz‐Dietrich Wuttke · 2008
Abstract. Automated test generation for digital systems encompasses three activities: selecting a description method, developing a fault model and generating tests to detect the faults covered by the fault model. The efficiency of test generation (quality, speed) is highly depending on the description method and fault models. As the complexity of digital systems continues to increase, the gate level test generation methods have become obsolete. Promising approaches are high-level methods. In this paper, a method for describing microprocessors as a special case of digital systems is explained and modeling faults with High-Level Decision Diagrams (HLDD) is presented. HLDDs serve as a basis for a general theory of test generation for mixed-level representations of systems, similarly as we have Boolean algebra for logic-level. HLDDs can be used for representing systems uniformly either at logic-level, highlevel or simultaneously at both levels. The fault model on HLDDs represents a generalization of the classical gatelevel stuck-at fault model to higher levels- the latter was defined for Boolean expressions whereas the former is defined for nodes in HLDDs having more general interpretation. 1.