Reversible Logic Synthesis by Iterative Compositions
Andrei B. Khlopotine, Marek A. Perkowski, Paweł Kerntopf · 2002
A reversible circuit maps each output vector into a unique input vector, and vice versa. CMOS reversible / adiabatic circuits are currently the most important approaches to power optimization. This paper introduces an approach to synthesize generalized multi-rail reversible cascades for singleoutput Boolean functions. Minimizing the “garbage bits” is the main challenge of reversible logic synthesis. Experimental results over a set of single output functions (derived from Espresso PLAs) will be presented at IWLS 2002.