Implementation of Vector Floating-point processing unit on FPGAs for high performance computing
Shi Chen, Ramachandran Venkatesan, Paul Gillard · Conference proceedings - Canadian Conference on Electrical and Computer Engineering · 2008
A vector floating point unit (VFPU) for high accuracy scientific computing is reported. The core module, a vector register file, is divided into eight lanes. One lane contains 16 vector registers, each including 16times32-bit elements, and is connected to a floating point adder and a floating point multiplier. A flag register is used to indicate the calculation sequence for the specific computing model. The prototype is implemented on Xilinx Virtex II Pro, and a peak performance of 3.020 GFLOPS at 188.768 MHz has been achieved.