A reconfigurable and high precision VLSI architecture for Fast Fourier Transform
Zhizhe Liu, Shunan Zhong · 2010
A reconfigurable and high precision FFT architecture is presented in this paper. The mixed radix-4/2 butterfly core is used in this architecture and the system can be configured as N=2n(n=5,6,7,8,9,10,11,12) size FFT. A data scaling approach is proposed and the Signal-to-Quantization Noise Radio (SQNR) can achieve up to 72.45dB when the system works at the 4096-point mode. Implementation of the proposed FFT architecture is under 0.18-µm signal-poly six-metal SMIC CMOS process. The power dissipation is 45mW at 20MHz.