Energy Efficient Memory Design using Low Voltage Complementary Metal Oxide Semiconductor on 28nm FPGA
Sweety, Minal Dhankar, Ravinder S. Kajal, Kartik Kalia, Kushagra Vashishta, Amit Kumar · Indian Journal of Science and Technology · 2015
In this work, we are designing a energy efficient memory circuit on 28nm FPGA. Four different LVCMOS are used to validate the energy efficient design. There is 40.67% power reduction when LVCMOS25 is used in place of LVCMOS33. LVCMOS25 is better than LVCMOS33 IO Standard according to our experiment. With LVCMOS15 there is 75.70% total power reduction in compare with the LVCMOS33. LVCMOS15 is most energy efficient IO Standard and LVCMOS33 is most power consuming IO Standard. To design a power efficient memory we are using Verilog as HDL, Xilinx ISE 14.6 simulator with kintex-7 FPGA. Keywords: Energy Efficient, FPGA, IO Standard, Low Power, LVCMOS, Memory