CAE functionality for verification of diagnostic programs
Carol Pyron, R.A. Sallade · 2003
A feasibility study that has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT (built-in-test) verification through fault simulation are described. With an example, the authors illustrate the evolutionary fault simulation features and the attendant methodology to support BIT verification by simulation. The simulator functionality and methodology will support the complex simulation of an embedded BIT program. These enhancements can also be effective in verification of ATE (automatic test equipment) functional tests for higher density integrated circuits and boards.>