Design and Test of a CMOS MLP Analog Neural Network for Fast On-Board Signal Processing
Laurent Gatet, HÉlÈne Tap-Beteille, Marc Lescure, Daniel Roviras, Alain Mallet · 2006
The feedforward Multi-Layer Perceptron (MLP) type Neural Network (NN) presented in this paper has been developed for on-board applications of high-speed signal processing (240 MHz). It is fully analog in order to avoid analog-digital conversions and to limit chip size and power consumption. It is constituted by a single input, ten neurons in the hidden layer and a single output. The MLP-NN has been implemented in a 84 pins -0.6μm CMOS ASIC. The NN layout size is 1.8mmx0.7mm and the consumption is intended less than 600mW. This paper presents the design and simulations of each implemented cell and the first experimental tests achieved on the implemented ASIC.