Hardware Implementation of LDPC Decoders
Christian Spagnol, Emanuel Mihai Popovici, William Peter Marnane · 2009
Low density parity check (LDPC) codes over are an extension of binary LDPC codes with significantly higher performance. However, the computational complexity of the encoders/decoders for these codes is also higher. Hence there is a substantial lack of hardware implementations for LDPC over codes. This paper proposes a novel variation of the belief propagation algorithm for LDPC codes. The new algorithm results in a reduced hardware complexity when imple- mented in VLSI. The serial architecture of the novel decoding algorithm and two other algorithms for LDPC over are implemented on an FPGA. The results show that the proposed algorithm has substantial advantages over existing methods. We show that the implementation of LDPC over decoder is feasible for short to medium length codes. The additional com- plexity of the decoder is balanced by the superior performance of LDPC codes.