Automatic generation of ModelSim-Matlab interface for RTL debugging and verification
Brian Gestner, David V. Anderson · Conference proceedings · 2007
We present a system Verilog/C code creation and compilation system that creates a ModelSim-Matlab shared memory interface optimized for the input/output specification of the user Verilog or VHDL. We describe how our interface approach is an improvement over the commercially available Mathworks Link for ModelSim, which requires the user to complete Verilog or VHDL data type conversion using slow m-files and to write interrupt-driven callback functions. Our interface approach frees the user from data type conversion and has the user write sequential test scripts but also takes advantage of a delayed-simulation execution technique to reduce simulation time. We demonstrate the utility of our interface approach by comparing a test script for a pipeline FFT processor to the corresponding Link for ModelSim version.