An analytical model for trace cache instruction fetch performance
A. Hossain, D.J. Pease · 2002
This paper presents an analytical model of instruction fetch performance of a trace cache. This paper also presents an analytical model of miss rate of a trace cache. These models can be used to analyze performance and behavior of a microarchitecture of a processor. These models are implemented in a new microarchitecture tool Tulip. Performances of several benchmark programs based on Tulip are also presented in this paper.