FPGA Implementation of Fir Filter using Distributed Arithmetic Architecture for DWT
Shruti S.Velukar, M. P. Parlewar · International Journal of Computer Applications · 2014
This paper presents an efficient FPGA implementation of Finite Impulse Response Filter for Discrete Wavelet Transform using Distributed Arithmetic architecture.This paper proposes a parallel implementation of FIR filter using Distributed Arithmetic Architecture, Distributed Arithmetic Architecture is a multiplier less architecture which uses Look-Up Table, ripple carry adder, shift registers.Distributed Arithmetic has an advantaged of less hardware, fast computation time.