PLD implements cache control for a 33-MHz 80486
J. Legenhausen · 2002
A no-wait-state, 33-MHz, 486 second-level cache controller, which usually requires a custom ASIC, has been implemented in a single PLD. The complexity of the design typifies what can be fit into current high-density PLDs for high-speed applications. A description of the design illustrates the necessary design techniques for this application.>