A Novel Method for Real-Time Data Sequence Compression of FPGA-Based SoC On-Chip Debugger
Guo-Ruey Tsai, Min‐Chuan Lin, Ming-Gia Gian · 대한전자공학회 ISOCC · 2006
We have presented a two-level trace compressor design with pipeline structure for real-time FPGAbased SoC on-chip debugger. A counter-based coarse level compressor is designed to cope with continuously repeating tracer data sequences, and the following fine level compressor is used to further compress the similarity bits between two neighbor trace of the derepeated tracer data sequence. The two-level trace compressor not only is synchronous with the tracer sampling clock rate, but also consume less synthesized chip area. The compression ratio of such a trace compressor is very high up to 100 times dependent of the tracer data channel arrangement. By the parametric hardware-description language module design, we can reconfigure flexible tracer data channel and data storage structure in order to match with different system requirements