A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip
TAKAO K. WATANABE, R. Fujita, Kazumasa Yanagisawa, H. Tanaka, Kazushige Ayukawa, M. Soga, Y. Tanaka, Y. Sugie, Y. Nakagome · 2002
Develops a modular architecture for a DRAM-integrated, multimedia chip, or media chip with a data transfer rate of 6 to 12 Gbyte/s. The DRAM macro enables the design flexibility both for DRAM capacity and the logic-memory interface to meet a wide variety of applications. A 6.4-Gbyte/s. 8-Mbit test chip was fabricated.