A new systolic squarer and its application to compute exponentiations in GF(2/sup m/)
Jyh-Huei Guo, Chin-Liang Wang · 2002
This paper presents a new systolic squarer and a new systolic exponentiator for GF(2/sup m/) with the standard basis representation. While computing squares in GF(2/sup m/), the proposed systolic squarer has smaller latency and less hardware requirement than a dedicated systolic multiplier. The proposed systolic exponentiator consists of [m/2] squarers, one multiplier, and [(m-1)/2] power-sum circuits (for AB/sup 2/+C). As compared to existing related exponentiators, it involves less hardware complexity and smaller latency. Both of the proposed architectures involve the features of regularity, modularity, and unidirectional data flow. As a consequence, they are well suited to VLSI implementation with fault-tolerant design.