80 MHz MCM microprocessor/cache subsystem based on i486 architecture
Robert C. Sundahl, M. Aghazadeh, Barry Lieberman, T.A. Schreyer, William Siu, Ricardo E. Suarez, J.D. Wilson · 2003
An experimental multichip module (MCM) implementation of a microprocessor/cache subsystem has been designed and demonstrated to operate at 80 MHz. The module consists of an 80486DX microprocessor with a cache controller and 256 kB of second-level cache (plus parity). Thus, the integration of 16 million transistors into a single 52-cm/sup 2/ package with single-chip performance has been achieved. The high performance of the module is dependent on the architecture, the MCM technology and the complex electrical, thermal, and mechanical simulation and routing tools developed for the task.>