Optimizing a superscalar machine to run vector code
Shlomo Weiss · IEEE Parallel & Distributed Technology Systems & Applications · 1993
A streamlined vector architecture and the IBM superscalar RISC System/6000 are discussed. It is shown, step-by-step, how each handles the same program. The factors that let vector machines outperform the RS/6000 are identified. Several extensions to the RS/6000 architecture that could help it attain vector-level performance on code with long vectors are proposed.>