CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs
Hamid Reza Zarandi, Seyed G. Miremadi, Dhiraj K. Pradhan, Jimson Mathew · 2007
This paper presents a SEU-mitigative placement and route of circuits in the FPGAs which is based on the popular placement and route tool. The tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation and no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. We have investigated the effect of this tool on several MCNC benchmarks and the results of the placement and routing have been compared to the traditional one. The evaluations of results show that placement and routing can decrease the SEU rate of circuits implemented on FPGAs about 22%. However, it increases critical path delay and power consumptions of the circuits.