Systolic Array Architecture Implementing Berlekamp–Massey–Sakata Algorithm for Decoding Codes on a Class of Algebraic Curves
Hajime Matsui, Shojiro Sakata, Masazumi Kurihara, S. Mita · IEEE Transactions on Information Theory · 2005
We construct a two-dimensional systolic array implementing the Berlekamp-Massey-Sakata (BMS) algorithm to provide error-locator polynomials for codes on selected algebraic curves. This array is constructed by introducing some new polynomials in order to increase the parallelism of the algorithm. The introduced polynomials are used in the majority logic scheme by Sakata et al. to correct errors up to the designed minimum distance without affecting its high speed. The arrangement of the nearest local connection of processing units in the systolic array is obtained for the general case. Furthermore, shortened systolic arrays that reduce the circuit scale and have the same function are constructed with only a slight modification of the connections and controls; this enables the adjustment of the circuit scale for different types of systems.