Task placement for heterogeneous reconfigurable architectures
Markus Koester, Mario Porrmann, Heiko Kalte · 2006
The concept of partial reconfiguration offers the possibility to dynamically place and remove hardware tasks on reconfigurable architectures, like FPGAs. Common placement algorithms, e.g. Best Fit, are designed for homogeneous architectures, since they do not consider any placement constraints of the hardware tasks. Due to the integration of, e.g., dedicated memory, current FPGAs are heterogeneous reconfigurable architectures. In this paper we introduce two heterogeneous placement algorithms, which are able to deal with the constraints of the hardware tasks. Both algorithms are compared to the Best Fit algorithm by using a simulation framework for partially configurable architectures. We propose concepts of an efficient hardware realization of our placement approach with Xilinx Virtex-II FPGAs. Moreover, we present a task placement mechanism to change the position of a hardware task on the FPGA by manipulating the configuration data of the task