BIST for embedded static RAMs with coverage calculation
J. van Sas, G. Van Wauwe, E. Huyskens, Dirk Rabaey · 2002
The implementation of deterministic RAM self-test algorithms turns out to be very area-consuming when a single ASIC contains many small, deeply embedded RAMs. Therefore, we have opted to reuse and modify the existing functional logic and to use a combined deterministic pseudo-random self-test strategy. A novel fault coverage calculation method for this self-test strategy has been developed. The method is easy to use because it is fully integrated in a hardware description language based design environment. Results for a chip set for broadband ISDN show that the combination of pseudo-random data generation and deterministic addressing of the RAMs provides high fault coverage results. Circuitry overhead varies between 2 and 14% of the RAM surface.>