CalmRISC/sup TM/-32: a 32-bit low-power MCU core
Sangyeun Cho, Sanghyun Park, Sang‐Woo Kim, Yong-Chun Kim, Seh-Woong Jeong, Bong-Young Chung, Hyung-Lae Roh, Changho Lee, Hun-Mo Yang, Sung-Ho Kwak, Moon-Key Lee · 2002
Architecting today's embedded processor core faces several important design challenges: low power, high performance, and system-on-a-chip considerations. Moreover, support for high-level language constructs and operating systems becomes increasingly critical for acceptance to various applications. CalmRISC/sup TM/-32 effectively meets these challenges by incorporating a carefully designed instruction set, an energy-efficient pipeline design, debugging support with trace mode/CalmBreaker/sup TM/ (an in-circuit debugger), and a generic, yet efficient coprocessor interface. Using a 0.25 /spl mu/m static CMOS standard cell library and compiled datapath cells, the first implementation of CalmRISC/sup TM/-32 operates at 130 MHz (under worst conditions) and consumes 150 /spl mu/A/MHz at 2.5 V. This paper presents a brief description of the instruction set, the overall microarchitecture, and the coprocessor interface of CalmRISC/sup TM/-32.