A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput
Rino Micheloni, Roberto Ravasio, Alessia Marelli, Electa Alice, V. Altieri, A. Bovino, Luca Crippa, E. Di Martino, L. D'Onofrio, Antonio Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, I. Motta, A. Prisco, G. Ragone, Mario Romano, Marco Sangalli, P. Sauro · 2006
A 4Gb 2b/cell NAND flash memory designed in a 90nm CMOS technology incorporates a 25MHz BCH ECC architecture, correcting up to 5 errors over a flexible data field (1B to 2102B). Two alternative Chien circuits are used depending on the number of errors (1 to 5) thus minimizing latency time. ECC area overhead is less than 1%