A 2.3-mW 16.7-MHZ ANALOG MATCHED FILTER CIRCUIT FOR DS-CDMA WIRELESS APPLICATIONS
Mostafa A. R. Eltokhy, Hala Abd El-kader Mansour · Progress In Electromagnetics Research B · 2008
Abstract—The matched filter (MF) is known as the fastest method for acquisition of DS-CDMA signals. Power consumption of the MF is a key issue for realizing multimedia hand-held terminals. We proposed a new Analog Matched Filter using Sample-and-Hold (S/H) circuit, which performs correlation between an input signal and a filtering coefficient employed for modulation in fully analog domain, eliminating the need to Analog-to-digital (A/D) conversion, so reduces power consumption and chip area. Simulation results reveal that the proposed circuit dissipates 2.3 mW power consumption at a chip rate of 16.7 MHz with 3.3 V power supply for 15 taps configuration. The proposed analog architecture could improve the performance of mobile terminals. 1.