A 100 MHz floating point/integer processor
George S. Taylor, A. Rekow, J. Radke, Gary W. Thompson · 2002
A single-chip floating point unit capable of 200 MFLOPS performance has been developed. The 20 ns latency of the ALU and multiplier units allows high scalar performance, not just high vector performance. The use of 64 b I/O ports allows sufficient I/O bandwidth to sustain this level of computation, while the chip may be configured with either one, two, or three pipeline registers, allowing it to conform to the degree of pipelining required in the user's system. A combination of commercial and proprietary tools were used. Verification of the layout match with its gate-level simulation model is a link provided by switch-level simulation in CMOS, but previously unavailable in bipolar designs. These tools also verify the correct use of series gating and the many reference voltages used in ECL designs.>