Multi-thread VLIW processor architecture for HDTV decoding
Han‐Soo Kim, Wooseung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In‐Cheol Park · 2002
This paper describes a single-chip high definition television (HDTV) decoder which performs system parsing, video decoding, audio decoding and resolution conversion. To process a huge amount of data and deal with various standards in the decoder, a multi-thread processor architecture is proposed to minimize the overhead cycles of task-switching. The features of parallelism and conditional branches in MPEG2 video decoding algorithm are considered to enhance the performance of the embedded processor and to reduce the size of code memory. Experimental results show that the proposed processor architecture is 5.3 times faster than a scalar processor at the cost of negligible increase of code memory.