A partitioning and storage based built-in test pattern generation method for synchronous sequential circuits
Irith Pomeranz, Sudhakar M. Reddy · 2002
We describe a built-in test pattern generation method for synchronous sequential circuits based on partitioning and storage of test subsequences. Under this method, a set of subsequences /spl Psi/ is stored on-chip. On-chip test sequences are obtained by implementing a subset of the Cartesian product /spl Psi/x/spl Psi/x/spl middot//spl middot//spl middot/x/spl Psi/. The set /spl Psi/ is obtained by iterative partitioning of a precomputed test sequence T. The number of subsequences in /spl Psi/ is minimized at every iteration in order to reduce the final storage requirements, the test application time, and the computational effort required to produce the final set /spl Psi/.