SH3: high code density, low power
Atsushi Hasegawa, Ikuya Kawasaki, Kazuji Yamada, S. Yoshioka, Shumpei Kawasaki, Partha Pratim Biswas · IEEE Micro · 1995
Hitachi's SH series microprocessors feature 32-bit RISC architecture with a 16-bit, fixed-length instruction set. We describe SH3, a pipelined implementation of the SH architecture with on-chip cache, MMU, and software-programmable power management. Its higher code density and corresponding improvement in instruction-fetch latency lead to higher performance than typical 32-bit RISC architectures achieve. These features, small die size, and low power consumption make SH3 an ideal microprocessor for portable computing systems or multimedia systems.