Application of quaternary logic to the design of a proposed discrete cosine transform chip
K.W. Current · International Journal of Electronics · 1989
Advantages of multiple-valued logic (MVL), such as reduced numbers of signal lines and increased functional density, are often accompanied by the disadvantage of reduced raw speed of operation. In some design situations, clock and throughput speeds are set by the application or design strategy. In such a situation, it may be possible to exploit the advantages of MVL without incurring the speed penalty. In this paper, we describe the design of a pipelined mathematical transform chip that can use MVL circuitry without speed penalty, requiring approximately 175% less silicon area than an all-binary version. CMOS quaternary threshold logic circuits are used in the design of the instruction memory and multiplier sections of the proposed single-chip implementation of a unified discrete cosine transform/ inverse discrete cosine transform (DCT/IDCT) architecture. This proposed MVL CMOS DCT/IDCT chip is projected to be capable of real-time processing of 10MHz video signals. In this paper, the unified DCT/IDCT architecture is summarized, and the use of quaternary logic circuits in a proposed DCT/IDCT chip design is described.