A novel BIST approach for testing logic resources using Hard Macro
Zhiquan Zhang, Zhiping Wen, Lei Chen, Fan Zhang, Tao Zhou · 2008
This paper explores an new Built-In Self-Test (BIST) approach to test the configurable logic blocks (CLBs) of Xilinx Virtex FPGAs using Hard Macro. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults as well as associated signal lines in the CLBs, while significantly reducing the Outputs needed to be compared by ORAs. Only 24 total test configurations for two sessions are required while retrieving the BIST results using scan chain method.