Power-conscious test synthesis and scheduling
Nicola Nicolici, Bashir M. Al‐Hashimi · IEEE Design & Test of Computers · 2003
BIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and test scheduling affect power dissipation and present new power-conscious algorithms.