Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory
S. Kobayashi, H. Nakai, Yuichi Kunori, T. Nakayama, Y. Miyawaki, Yasushi Terada, Hiroshi Onoda, N. Ajika, M. Hatanaka, Hirokazu Miyoshi, Tatsuhiko Yoshihara · IEEE Journal of Solid-State Circuits · 1994
A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V/sub cc/ and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 /spl mu/m, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8/spl times/1.6 /spl mu/m/sup 2/ and the chip measures 5.8/spl times/5.0 mm/sup 2/. The divided bit line structure realizes a small NOR type memory cell.>